Memory device, memory system having the same and method of operating the same
US11922989B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 20, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Sep 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.