Semiconductor package including a trench in a passivation layer
US11923314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | May 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a connection structure including a redistribution layer, a plurality of under bump metal layers electrically connected to the redistribution layer, a passivation layer which overlaps at least portions of side faces of the plurality of under bump metal layers, and includes a first trench disposed between under bump metal layers adjacent to each other, a surface mounting element which is on the under bump metal layers adjacent to each other, connected to the redistribution layer, and overlaps the first trench, and an underfill material layer that is between a portion of the passivation layer and the surface mounting element, and is in the first trench. The first trench extends in a first direction and includes a first sub-trench having a first width in a second direction, and a second sub-trench having a second width different from the first width in the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.