Stacked-chip packages having through vias
US11923351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Jan 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.