Electronic integration circuit having offset and collected charge reduction circuitries and associated methods
US11923815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Jun 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrator having an offset evaluation circuit and a collected charge reduction circuitry and method for using the integrator. The integrator includes an amplifier, operable to amplify an input signal, an integration capacitor for collecting charge indicative of a level of the input signal and an offset capacitor. The offset evaluation circuit is operable to charge the offset capacitor with charge corresponding to an offset voltage of the amplifier and the collected charge reduction circuitry is operable to collect charge resulting from disconnection of the offset evaluation circuit, thereby reducing an amount of charge and associated noise input to the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.