Integrated circuit, dynamic voltage and frequency scaling (DVFS) governor, and computing system including the same
US11927981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2022 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | May 20, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.