Quantum error mitigation based on scaled gates
US11928004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques regarding quantum error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that can add a set of scaled quantum gates to a quantum circuit for error mitigation. The set of scaled quantum gates can comprise a quantum gate and an inverse of the quantum gate. Also, the set of scaled quantum gates can have a rotation angle based on a pulse schedule to achieve a target stretch factor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.