Monitoring processors operating in lockstep
US11928007B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2020 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Nov 25, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.