Implementing erasure coding with persistent memory
US11928497B2 · kind B2 · utility
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18References
20Claims
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Key dates
| Filing date | Jan 27, 2020 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Oct 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method according to one embodiment includes receiving a request to perform a transaction in persistent memory at a first node; implementing the transaction within a volatile transaction cache at the first node; determining parity data for the transaction at the first node; sending the parity data from the first node to a parity node; and transferring results of the transaction from the volatile transaction cache to the persistent memory at the first node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.