Wafer level package and method of manufacture
US11929729B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2019 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Jul 10, 2040 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B2207/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A wafer level package comprises a functional wafer with a first surface, device structures connected to device pads arranged on the first surface. A cap wafer, having an inner and an outer surface, is bonded with the inner surface to the first surface of the functional wafer. A frame structure surrounding the device structures is arranged between functional wafer and cap wafer. Connection posts are connecting the device pads on the first surface to inner cap pads on the inner surface. Electrically conducting vias are guided through the cap wafer connecting inner cap pads on the inner surface and package pads on the outer surface of the cap wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.