Successive approximation register analog-to-digital converter for wide sampling rate
US11929758B2 · kind B2 · utility
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5References
10Claims
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Key dates
| Filing date | Mar 19, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Mar 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate includes a first PMOS switch controlled by a voltage of a second control node, second PMOS switch controlled by a control voltage, a first control switch unit controlling voltages of first and second control nodes, a first NMOS switch controlled by a voltage of a fourth control node, a second NMOS switch controlled by the control voltage und, and a second control switch unit controlling voltages of third and fourth control nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.