Low density parity check decoder and storage device
US11929762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2022 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Aug 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.