Circuit configured to compensate for timing skew and operation method thereof
US11929772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Oct 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/364
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An electronic circuit converts a receive signal being analog into reception data being digital. The electronic circuit includes a delay circuit that receives a first receive signal and outputs a reference signal, the reference signal being generated by delaying the first receive signal as much as one of a plurality of different timing delays respectively set to a plurality of loops, a sampler that receives a second receive signal and samples the second receive signal based on the reference signal in each of the plurality of loops, a timing skew estimation circuit that outputs a compensation signal for compensating for a timing skew by extracting a statistical characteristic of a plurality of sample data sampled through the sampler and estimating the timing skew based on the statistical characteristic, and a controller that controls an operation of the timing skew estimation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.