Semiconductor memory device including multiple conductive line layers
US11930629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | May 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.