Resistive memory device
US11930646B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Aug 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/882
Abstract
A resistive memory device includes a plurality of first conductive lines in a first area and a second area on a substrate, a plurality of second conductive lines in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, and a plurality of memory cells connected to the first and second conductive lines at a plurality of intersections between the plurality of first and second conductive lines in the first area and the second area. The plurality of memory cells include an active memory cell in the first area and a dummy memory cell in the second area. The active memory cell including a first resistive memory pattern having a first width and the dummy memory cell including a second resistive memory pattern having a second width greater than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.