Array substrate, preparation method therefor, and display device
US11930679B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 12, 2020 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Nov 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
Abstract
The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.