Fabrication method of a double-gate carbon nanotube transistor
US11930696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Jul 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K10/491
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.