Power electronics assembly having staggered and diagonally arranged transistors
US11932114B2 · kind B2 · utility
0Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2020 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Oct 26, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T10/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses and systems to provide for technology to that includes a first power electronics module including a plurality of first transistors that are diagonally offset from each other, and a second power electronics module stacked on the first power electronics module. The second power electronics module includes second transistors that are diagonally offset from each other. The second transistors are staggered relative to the first transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.