Partitioning responsive to processors having a disparate number of memory modules
US11934661B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Dec 22, 2022 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Dec 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments provide a method and computer program product including program instructions executable by a baseboard management controller in a multi-processor system to perform various operations. The operations include detecting a number of memory modules connected to each of a plurality of central processing units (CPUs) in the multi-processor system during boot, initiating operation of the multi-processor system as a single unified node in response to each of the CPUs being connected to an equal number of memory modules, and initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the CPUs each being connected to a first number of memory modules and a second set of one or more of the CPUs each being connected to a second number of memory modules that is different than the first number of memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.