Voltage impacts on delays for timing simulation
US11934760B1 · kind B1 · utility
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2References
20Claims
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Key dates
| Filing date | Dec 23, 2021 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Aug 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.