Physical interface and associated signal processing method for clock domain transfer of quarter-rate data
US11935577B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Feb 8, 2022 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Sep 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.