Method of manufacturing a semiconductor structure, and a semiconductor structure
US11935785B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2021 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Nov 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure includes: providing a base and a dielectric layer on the base, the base in an array region being provided with discrete capacitive contact plugs and a first conductive layer being formed on a top surface of the capacitive contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, the target layer in the array region and the first circuit region being provided with first openings through the target layer; patterning the target layer in the array region as well as in the first circuit region and the second circuit region to form a second opening and a third opening; etching the conversion layer to form a first trench; forming a filling layer filling the first trench and removing the conversion layer to form a second trench filled by a second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.