Integrated filler capacitor cell device and corresponding manufacturing method
US11935828B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2023 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Mar 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.