Buffer apparatus, chip and electronic device
US11936375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2022 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Apr 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer apparatus, a chip and an electronic device. The apparatus comprises: a voltage adjustment module (10) comprising a first P-type metal-oxide-semiconductor field-effect transistor (PMOS), wherein the voltage adjustment module (10) is used for receiving an input voltage, using a threshold voltage for the first PMOS to adjust the input voltage, and outputting a driving voltage; and a buffer module (20) electrically connected to the voltage adjustment module (10) and used for receiving an input signal, buffering the input signal under the driving voltage, and outputting a buffered signal. The driving voltage obtained by using the threshold voltage for the first PMOS to adjust the input voltage can compensate for a process corner of the buffer module (20), such that the range of a flip point voltage of the buffer module (20) becomes small and meets process requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.