Multi-bit flip-flop circuit with reduced area and reduced wire complexity
US11936384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2023 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Jan 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-bit flip-flop includes a first bit flip-flop and a second bit flip-flop. The first bit flip-flop includes an input multiplexer that receives a first and second data bits, and outputs one of the first and second data bits as a third data bit; a first transmission circuit; a first latch; a second transmission circuit; and a second latch that outputs a first output data bit. The second bit flip-flop includes an input multiplexer that receives a fourth data bit and the first output data bit, and outputs one of the fourth data bit and the first output data bit as a fifth data bit; a first transmission circuit, a first latch, a second transmission circuit, and a second latch that outputs a second output data bit. The first output data bit is provided from the first bit flip-flop to the second bit flip-flop along an external wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.