Semiconductor devices including separate charge storage layers
US11937425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Aug 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/694
Abstract
Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.