Clock disciplining and synchronizing
US11940835B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Oct 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment may involve receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator; reading the local time value and writing it to a memory as a current time value; determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock; based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and modifying the local time increment by the adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.