Error correction code validation
US11940872B2 · kind B2 · utility
0Cited by
19References
19Claims
0Family size
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Key dates
| Filing date | Apr 21, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Apr 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.