Cross address-space bridging
US11940933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2021 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Jul 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.