Heterogeneous integration semiconductor package structure
US11942396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2021 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Jul 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer. The circuit substrate is electrically connected to the second redistribution structure layer of the package assembly through the connectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.