Method of manufacturing a semiconductor package
US11942434B2 · kind B2 · utility
0Cited by
20References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.