Electrostatic discharge protection for high speed transceiver interface
US11942473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Jun 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.