High-speed level-shifter for power-conversion applications
US11942942B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Dec 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/603
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit uses standard n-channel and p-channel transistors except for a pair of Lateral-Diffusion Metal-Oxide-Semiconductor (LDMOS) transistors that have an added lateral diffusion under the gate between the source and the conduction channel, increasing the breakdown voltage. The source of each LDMOS transistor connects to a drain of a transient differential transistor that has its gate driven by a oneshot that generates a pulse after an input transition. After the pulse ends a holding differential transistor draws a smaller bias current from the LDMOS transistors. The source of each LDMOS transistor connects to the drain and gate of a p-channel sensing transistor that drives gates of mirror transistors generating mirrored currents to cross-coupled n-channel mirror transistors that drive both terminals of a bistable latch that holds the output using a floating ground between driver transistors of a Buck converter switched by the bistable latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.