Input clock buffer and clock signal buffereing method
US11942950B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Nov 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00176
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.