Time-to-digital converter and digital phase-locked loop circuit comprising the same
US11942956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Sep 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1014
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.