Compression circuits and methods using tree based encoding of bit masks
US11942970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Mar 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/405
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure include techniques for compressing data using a tree encoded bit mask that may result in higher compression ratios. In one embodiment, an input vector having a plurality of values is received by a first plurality of switch circuits. Selection of the input values is controlled by sets of bits from the bit mask. The sets of bits specify locations of portions of the input vector where particular value of interest reside. The switch circuits output multiple values of the input vector, which include the particular value of interest. A second stage of switch circuits is controlled by logic circuit that detects values on the outputs of the first stage of switch circuits and outputs the values of interest. In some embodiments, the values of interest may be non-zero values of a sparse input vector, and the switch circuits may be multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.