Method and system for testing conversion relationship between block reading and page reading in flash memory chip
US11947819B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 27, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | May 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and device for testing a conversion relationship between different reading manners in a flash memory chip and a readable storage medium are provided. Block reading is respectively performed, a bit error rate file is recorded, a test starting point, a test ending point and a test step length are is set in a block, the bit error rate file of the number of times of corresponding page reading is respectively recorded, and the number of times of page reading that is closest to the proportion of block error codes are found from the proportion of page error codes, a conversion of the number of times of block reading and the number of times of page reading is completed, conversion coefficients of the block reading and the page reading can be calculated for blocks in different states of a life cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.