Chips placed in full-custom layout and electronic device for implementing mining algorithm
US11947889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.