Semiconductor structure and manufacturing method thereof
US11948616B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Dec 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.