Memory devices, memory systems having the same, and operating methods thereof
US11948621B2 · kind B2 · utility
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16References
20Claims
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Key dates
| Filing date | Jun 14, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Oct 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.