Memory device
US11948636B2 · kind B2 · utility
0Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/75
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.