Sub-cell, mac array and bit-width reconfigurable mixed-signal in-memory computing module
US11948659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Aug 5, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. A MAC array for performing MAC operations, includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. A differential version of the MAC array provides improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, allowing the computing module to have a reduced area and suffer from fewer computational errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.