Method and system for etch depth control in III-V semiconductor devices
US11948801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Nov 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.