Etching method, air-gap dielectric layer, and dynamic random-access memory
US11948805B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An etching method for selectively etching a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.