Integrated circuit device
US11948942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2023 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Mar 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.