Patent · US Active

Low-power pulse output circuit

US11949409B2 · kind B2 · utility

0Cited by

3References

4Claims

0Family size

Assignee

Wenzhou University · CN

Inventors

Xiangyu Li · Longbeilingcun, CN
Pengjun Wang · Zhejiang, CN
Gang Li · Beijing, CN

Key dates

Filing date	Jan 9, 2023
Grant date	Apr 2, 2024
Priority date	—
Expiry date	Jan 9, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/00
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A low-power pulse output circuit comprises first to third PMOS transistors, first NMOS to third NMOS transistors, a resistor regulation module, a capacitor regulation module, an inverter and a buffer. Drains of the first PMOS and first NMOS transistors, gates of the first NMOS, second PMOS, second NMOS, and third NMOS transistors are connected. Drain of the second PMOS transistor, gate of the third PMOS transistor and one terminal of the resistor regulation module are connected. The other terminal of the resistor regulation module and drain of the second NMOS transistor are connected. Drain of the third PMOS transistor, drain of the third NMOS transistor and an input terminal of the inverter are connected. An output terminal of the inverter, the other terminal of the capacitor regulation module and an input terminal of the buffer are connected.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.