Method and procedure for miniaturing a multi-layer PCB
US11950361B2 · kind B2 · utility
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7References
6Claims
0Family size
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Key dates
| Filing date | Sep 16, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Sep 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09327
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include signal layers, ground plane layers, inner signal layers, and a single core substrate layer. Each of the layers may be separated from the other layers by at least one prepreg substrate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.