Semiconductor device
US11950417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Sep 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.