Three-dimensional semiconductor memory devices
US11950517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | May 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
Abstract
A three-dimensional semiconductor memory device may include a first conductive line extending in a first direction, a second conductive line extending in a second direction crossing the first direction, a cell stack at an intersection of the first and second conductive lines, and a gapfill insulating pattern covering a side surface of the cell stack. The cell stack may include first, second, and third electrodes sequentially stacked, a switching pattern between the first and second electrodes, and a variable resistance pattern between the second and third electrodes. A top surface of the gapfill insulating pattern may be located between top and bottom surfaces of the third electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.