Data-driven column-wise clock gating of systolic arrays
US11953966B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Jul 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and corresponding systems and apparatuses for saving power through selectively disabling clock signals in a systolic array are described. In some embodiments, a clock gate controller is operable to output a gated clock signal from which local clock signals of processing elements in the systolic array are derived. The gated clock signal corresponds to a root clock signal that is distributed through a clock distribution network or clock tree. The clock gate controller is located along one branch of the clock distribution network. The branch can be associated with processing elements that form a column within the systolic array. Disabling the gated clock signal disables the local clock signals along the entire branch, preventing any components that are clocked by those local clock signals from consuming power. Additional clock gate controllers can similarly be provided for other branches, including a branch associated with another column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.