Peripheral component interconnect express device error reporting optimization method and system capable of filtering error reporting messages
US11953975B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Nov 24, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral component interconnect express (PCIe) device error reporting optimization method includes acquiring advanced error reporting data of a PCIe device, executing a removal detection process of the PCIe device for detecting if the PCIe device is plugged into a connector, transmitting error log data of the PCIe device to a baseboard management controller and an advanced configuration and power interface according to the advanced error reporting data if the PCIe device is plugged into the connector, and filtering the error log data of the PCIe device so that filtered error log data is received by the baseboard management controller and the advanced configuration and power interface if the PCIe device and the connector are electrically disconnected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.